ARM Cortex-A35 User Manual

B1.26 AArch32 Performance monitor registers
The following table shows the performance monitor registers.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information.
Table B1-25 Performance monitor registers
Name CRn Op1 CRm Op2 Reset Description
PMCR c9 0 c12 0
0x410A3000
C10.2 Performance Monitors Control Register on page C10-692
PMCNTENSET 1 UNK
Performance Monitors Count Enable Set Register
PMCNTENCLR 2 UNK
Performance Monitors Count Enable Clear Register
PMOVSR 3 UNK
Performance Monitors Overflow Flag Status Register
PMSWINC 4 UNK
Performance Monitors Software Increment Register
PMSELR 5 UNK
Performance Monitors Event Counter Selection Register
PMCEID0 6
0x6FFFBFFF
C10.3 Performance Monitors Common Event Identification Register 0
on page C10-695
The reset value is 0x6E3FBFFF if L2 cache is not implemented.
PMCEID1 7
0x00000000
C10.4 Performance Monitors Common Event Identification Register 1
on page C10-699
PMCCNTR c13 0 UNK
Performance Monitors Cycle Count Register
PMXEVTYPER 1 UNK Performance Monitors Selected Event Type Register
PMXEVCNTR 2 UNK
Performance Monitors Event Count Registers
PMUSERENR c14 0
0x00000000
Performance Monitors User Enable Register
PMINTENSET 1 UNK
Performance Monitors Interrupt Enable Set Register
PMINTENCLR 2 UNK Performance Monitors Interrupt Enable Clear Register
PMOVSSET 3 UNK
Performance Monitor Overflow Flag Status Set Register
B1 AArch32 system registers
B1.26 AArch32 Performance monitor registers
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English