ARM Cortex-A35 User Manual

B2.33 Architectural Feature Trap Register, EL3
The CPTR_EL3 characteristics are:
Purpose
Controls trapping to EL3 for accesses to CPACR, Trace functionality and registers associated
with Advanced SIMD and floating-point execution. Controls EL3 access to this functionality.
CPTR_EL3 is part of the Security registers functional group.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
Configurations
There are no configuration notes.
Attributes
CPTR_EL3 is a 32-bit register.
31 0
RES0 RES0
TFP
10 91130
TCPAC
192021
RES0
TTA
121314
Figure B2-8 CPTR_EL3 bit assignments
TCPAC, [31]
This causes a direct access to the CPACR_EL1 from EL1 or the CPTR_EL2 from EL2 to trap to
EL3 unless it is trapped at EL2. The possible values are:
0 Does not cause access to the CPACR_EL1 or CPTR_EL2 to be trapped.
1 Causes access to the CPACR_EL1 or CPTR_EL2 to be trapped.
[30:21]
Reserved, RES0.
TTA, [20]
Trap Trace Access.
Not implemented. RES0.
[19:11]
Reserved, RES0.
TFP, [10]
This causes instructions that access the registers associated with Advanced SIMD or floating-
point execution to trap to EL3 when executed from any exception level, unless trapped to EL1
or EL2. The possible values are:
B2 AArch64 system registers
B2.33 Architectural Feature Trap Register, EL3
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B2-406
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English