ARM Cortex-A35 User Manual

A.13 CHI interface signals
The CHI protocol supports clock, configuration, data handling, and address map signals when the
processor uses this protocol for the master memory interface.
This interface exists only if the processor is configured to have the CHI interface.
Table A-34 CHI clock and configuration signals
Signal Direction Description
SCLKEN Input CHI interface bus clock enable
SINACT Input CHI snoop active
NODEID[6:0] Input Cortex‑A35 CHI Node Identifier
RXSACTIVE Input Receive pending activity indicator
TXSACTIVE Output Transmit pending activity indicator
RXLINKACTIVEREQ Input Receive link active request
RXLINKACTIVEACK Output Receive link active acknowledge
TXLINKACTIVEREQ Output Transmit link active request
TXLINKACTIVEACK Input Transmit link active acknowledge
REQMEMATTR[7:0] Output Request memory attributes
Table A-35 CHI transmit request virtual channel signals
Signal Direction Description
TXREQFLITPEND Output Transmit request flit pending
TXREQFLITV Output Transmit request flit valid
TXREQFLIT[99:0] Output Transmit request flit payload
TXREQLCRDV Input Transmit request link-layer credit valid
Table A-36 CHI transmit response virtual channel signals
Signal Direction Description
TXRSPFLITPEND Output Transmit response flit pending
TXRSPFLITV Output Transmit response flit valid
TXRSPFLIT[44:0] Output Transmit response flit
TXRSPLCRDV Input Transmit response link-layer credit valid
Table A-37 CHI transmit data virtual channel signals
Signal Direction Description
TXDATFLITPEND Output Transmit data flit pending
TXDATFLITV Output Transmit data flit valid
TXDATFLIT[193:0] Output Transmit data flit
TXDATLCRDV Input Transmit data link-layer credit valid
A Signal Descriptions
A.13 CHI interface signals
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
Appx-A-868
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English