A4.10 Powering down the processor with system driven L2 flush
When powering down the processor, the PDMERCURY, PDL2, and PDCPU power domains are shut
down and all state is lost.
To power down the cluster, apply the following sequence:
Procedure
1. Ensure all cores are in shutdown mode, see A4.6 Powering down an individual core on page A4-65.
2. If the ACP interface is configured, ensure that any master connected to the interface does not send
new transactions, then assert AINACTS. This is necessary to prevent ACP transactions from
allocating new entries in the L2 cache while the hardware cache flush is occurring.
3. Assert L2FLUSHREQ HIGH.
4. Hold L2FLUSHREQ HIGH until L2FLUSHDONE is asserted.
5. Deassert L2FLUSHREQ.
6. In an ACE configuration, assert ACINACTM or, in a CHI configuration, assert SINACT. Then, wait
until the STANDBYWFIL2 output is asserted to indicate that the L2 memory system is idle. All
Cortex‑A35 processor implementations contain an L2 memory system, including implementations
without an L2 cache. This applies to implementations that use the mini-SCU and implementations
that use the SCU.
7. Activate the cluster output clamps.
8. Remove power from the PDMERCURY and PDL2 power domains.
A4 Power Management
A4.10 Powering down the processor with system driven L2 flush
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A4-69
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