B1.75 Instruction Set Attribute Register 1
The ID_ISAR1 characteristics are:
Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR0, ID_ISAR2, ID_ISAR3, ID_ISAR4 and ID_ISAR5. See:
• B1.74 Instruction Set Attribute Register 0 on page B1-269
• B1.76 Instruction Set Attribute Register 2 on page B1-273
• B1.77 Instruction Set Attribute Register 3 on page B1-275
• B1.78 Instruction Set Attribute Register 4 on page B1-277
• B1.79 Instruction Set Attribute Register 5 on page B1-279
Configurations
ID_ISAR1 is architecturally mapped to AArch64 register ID_ISAR1_EL1. See B2.58 AArch32
Instruction Set Attribute Register 1, EL1 on page B2-457.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_ISAR1 is a 32-bit register.
31
28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Jazelle Interwork Immediate IfThen Extend Except_AR Except Endian
Figure B1-30 ID_ISAR1 bit assignments
Jazelle, [31:28]
Indicates the implemented Jazelle state instructions:
0x1 The BXJ instruction, and the J bit in the PSR.
Interwork, [27:24]
Indicates the implemented Interworking instructions:
0x3 • The BX instruction, and the T bit in the PSR.
• The BLX instruction. The PC loads have BX-like behavior.
• Data-processing instructions in the A32 instruction set with the PC as the
destination and the S bit clear, have BX-like behavior.
Immediate, [23:20]
Indicates the implemented data-processing instructions with long immediates:
B1 AArch32 system registers
B1.75 Instruction Set Attribute Register 1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-271
Non-Confidential
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