B2.3 AArch64 Exception handling registers
The following table shows the fault handling registers in AArch64 state.
Bits[63:32] are reset to 0x00000000 for all 64-bit registers in the table.
Table B2-2 AArch64 exception handling registers
Name Type Reset Width Description
AFSR0_EL1 RW
0x00000000
32 B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 on page B2-391
AFSR1_EL1 RW
0x00000000
32 B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392
ESR_EL1 RW UNK 32 B2.41 Exception Syndrome Register, EL1 on page B2-423
IFSR32_EL2 RW UNK 32 B2.69 Instruction Fault Status Register, EL2 on page B2-479
AFSR0_EL2 RW
0x00000000
32 B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 on page B2-391
AFSR1_EL2 RW
0x00000000
32 B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392
ESR_EL2 RW UNK 32 B2.42 Exception Syndrome Register, EL2 on page B2-425
AFSR0_EL3 RW
0x00000000
32 B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 on page B2-391
AFSR1_EL3 RW
0x00000000
32 B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392
ESR_EL3 RW UNK 32 B2.43 Exception Syndrome Register, EL3 on page B2-427
FAR_EL1 RW UNK 64 B2.44 Fault Address Register, EL1 on page B2-429
FAR_EL2 RW UNK 64 B2.45 Fault Address Register, EL2 on page B2-430
HPFAR_EL2 RW
0x0000000000000000
64 B2.49 Hypervisor IPA Fault Address Register, EL2 on page B2-440
FAR_EL3 RW UNK 64 B2.46 Fault Address Register, EL3 on page B2-431
VBAR_EL1 RW UNK 64 B2.100 Vector Base Address Register, EL1 on page B2-551
ISR_EL1 RO UNK 32 B2.72 Interrupt Status Register, EL1 on page B2-484
VBAR_EL2 RW UNK 64 B2.101 Vector Base Address Register, EL2 on page B2-552
VBAR_EL3 RW UNK 64 B2.102 Vector Base Address Register, EL3 on page B2-553
B2 AArch64 system registers
B2.3 AArch64 Exception handling registers
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