C6.4 Debug ID Register
The DBGDIDR characteristics are:
Purpose
Specifies:
• The version of the Debug architecture that is implemented.
• Some features of the debug implementation.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
RO RO RO RO RO RO RO
Configurations
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
See C6.1 AArch32 debug register summary on page C6-620.
31
28 27 24 23 20 19 16 15 14 13 12 11 0
WRPs BRPs CTX_CMPs Version RES0
DEVID_imp
PCSR_imp
SE
nSUHD_imp
Figure C6-3 DBGDIDR bit assignments
WRPs, [31:28]
The number of Watchpoint Register Pairs (WRPs) implemented. The number of implemented
WRPs is one more than the value of this field. The value is:
0x3 The processor implements 4 WRPs.
This field has the same value as ID_AA64DFR0_EL1.WRPs.
BRPs, [27:24]
The number of Breakpoint Register Pairs (BRPs) implemented. The number of implemented
BRPs is one more than the value of this field. The value is:
0x5 The processor implements 6 BRPs.
This field has the same value as ID_AA64DFR0_EL1.BRPs.
CTX_CMPs, [23:20]
The number of BRPs that can be used for Context matching. This is one more than the value of
this field. The value is:
0x1 The processor implements two Context matching breakpoints, breakpoints 4 and 5.
This field has the same value as ID_AA64DFR0_EL1.CTX_CMPs.
Version, [19:16]
The Debug architecture version.
C6 AArch32 debug registers
C6.4 Debug ID Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C6-628
Non-Confidential
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