A11.3 ACP performance
The ACP interface can support up to four outstanding transactions. These can be any combination of
reads and writes.
The master must avoid sending more than one outstanding transaction on the same AXI ID, to prevent
the second transaction stalling the interface until the first has completed. If the master requires explicit
ordering between two transactions, Arm recommends that it waits for the response to the first transaction
before sending the second transaction.
Writes are higher performance when they contain a full cache line of data.
If SCU cache protection is configured, writes of less than 64 bits incur an overhead of performing a read-
modify-write sequence if they hit in the L2 cache.
Some L2 resources are shared between the ACP interface and the cores, therefore heavy traffic on the
ACP interface might, in some cases, reduce the performance of the cores.
AXI and
ACE
You can use the ARCACHE and AWCACHE signals to control whether the ACP request
causes an allocation into the L2 cache if it misses.
CHI To ensure correct ordering of data beats, ACP reads that miss always allocate into the L2
cache.
A11 ACP Slave Interface
A11.3 ACP performance
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A11-138
Non-Confidential
To Next Page
Loading...
Need help?
General
