A5.8 Error reporting
The processor reports detected errors, including errors that are successfully corrected and those that
cannot be corrected, in the CPUMERRSR or L2MERRSR registers. It also signals them on the
PMUEVENT bus.
If multiple errors occur on the same clock cycle then only one of them is reported. Errors that cannot be
corrected, and therefore might result in data corruption, also cause an abort or external pin to be asserted,
so that software can be aware that there is an error and can either attempt to recover or can restart the
system. Such errors are:
• Uncorrectable errors in the L2 data RAM when read by an instruction fetch, TLB pagewalk, or load
instruction, might result in a precise data abort or prefetch abort.
• Uncorrectable errors in the L2 data RAM when read by a fetch into the L1 data cache from a load,
store or preload instruction, or by the hardware prefetcher, might result in an asynchronous exception.
• Uncorrectable errors in the L1 or L2 data RAMs when the line is being evicted from a cache results
in the processor asserting the nINTERRIRQ signal. This might be because of a natural eviction, a
cache maintenance operation, or a snoop.
• Uncorrectable errors in the L2 tag RAMs or SCU L1 duplicate tag RAMs result in the processor
asserting the nINTERRIRQ signal.
• When nINTERRIRQ is asserted it remains asserted until the error is cleared by a write of 0 to the L2
internal asynchronous error bit of the L2ECTLR register.
• Arm recommends that the nINTERRIRQ signal is connected to the interrupt controller so that an
interrupt or system error is generated when the signal is asserted.
When a dirty cache line with an error on the data RAMs is evicted from the processor, the write on the
master interface still takes place, however if the error is uncorrectable then:
• On AXI and ACE, the write strobes are not set, therefore the incorrect data is not written externally.
• On CHI, the strobes are set, but the response field indicates that there is a data error.
When a snoop hits on a line with an uncorrectable data error the data is returned, if required by the
snoop, but the snoop response indicates that there is an error.
If a snoop hits on a tag that has an uncorrectable error, then it is treated as a snoop miss, because the error
means that it is unknown if the cache line is valid or not.
In some cases it is possible for an error to be counted more than once. For example, multiple accesses
might read the location with the error before the line is evicted as part of the correction process.
Related reference
B1.44 CPU Memory Error Syndrome Register on page B1-214
B1.93 L2 Extended Control Register on page B1-305
B1.94 L2 Memory Error Syndrome Register on page B1-307
A5 Cache Behavior and Cache Protection
A5.8 Error reporting
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A5-86
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