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General| Architecture | ARMv6-M |
|---|---|
| Data Bus Width | 32-bit |
| Clock Speed | Up to 50 MHz |
| Interrupts | Nested Vectored Interrupt Controller (NVIC) |
| Number of Cores | 1 |
| Memory Protection | Optional Memory Protection Unit (MPU) |
| Interrupt Controller | Nested Vectored Interrupt Controller (NVIC) |
| Pipeline | 3-stage |
| Max Clock Speed | 50 MHz |
| Instruction Set | Thumb |
| Power Consumption | Low power design |
| Debug | Serial Wire Debug (SWD) |
| Die Size | Implementation dependent |
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