ARM Cortex-M0 User Manual

Introduction
1-6 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
1.5 Product documentation, design flow and architecture
This section describes the processor books, how they relate to the design flow, and the
relevant architectural standards and protocols.
See Additional reading on page xiii for more information about the books described in
this section.
1.5.1 Documentation
This section describes the documents for the processor.
Technical Reference Manual
The Technical Reference Manual (TRM) describes the functionality and
the effects of functional options on the behavior of the processor. It is
required at all stages of the design flow. The choices made in the design
flow can mean that some behavior described in the TRM is not relevant.
If you are programming the processor then contact:
• the implementer to determine:
— the build configuration of the implementation
— what integration, if any, was performed before implementing
the processor
• the integrator to determine the input configuration of the device
that you are using.
Integration and Implementation Manual
The Integration and Implementation Manual (IIM) describes:
• The available build configuration options and related issues in
selecting them.
• How to configure the Register Transfer Level (RTL) with the build
configuration options.
• How to integrate the processor into a SoC. This includes describing
the pins that the integrator must tie off to configure the macrocell
for the required integration.
• The processes to sign off the integration and implementation of the
design.
The ARM product deliverables include reference scripts and information
about using them to implement your design.
Reference methodology documentation from your EDA tools vendor
complements the IIM.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent