ARM Cortex-M0 User Manual

Programmers Model
3-2 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
3.1 About the programmers model
The ARMv6-M ARM provides a complete description of the programmers model. This
chapter gives an overview of the Cortex-M0 programmers model that describes the
implementation-defined options. It also contains the ARMv6-M Thumb instructions it
uses and their cycle counts for the processor. In addition:
• Chapter 4 summarizes the system control features of the programmers model
• Chapter 5 summarizes the NVIC features of the programmers model
• Chapter 6 summarizes the Debug features of the programmers model.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent