ARM Cortex-M0 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 5-3
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5.2 NVIC register summary
Table 5-1 shows the NVIC registers. Each of these registers is 32 bits wide.
Note
See the ARMv6-M ARM for more information about the NVIC registers and their
addresses, access types, and reset values.
Table 5-1 NVIC registers
Name Description
ISER Interrupt Set-Enable Register in the ARMv6-M ARM
ICER Interrupt Clear-Enable Register in the ARMv6-M ARM
ISPR Interrupt Set-Pending Register in the ARMv6-M ARM
ICPR Interrupt Clear-Pending Register in the ARMv6-M ARM
IPR0-IPR7 Interrupt Priority Registers in the ARMv6-M ARM

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent