ARM Cortex-M0 - 5.2 NVIC register summary

Nested Vectored Interrupt Controller
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5.2 NVIC register summary
Table 5-1 shows the NVIC registers. Each of these registers is 32 bits wide.
Note
See the ARMv6-M ARM for more information about the NVIC registers and their
addresses, access types, and reset values.
Table 5-1 NVIC registers
Name Description
ISER Interrupt Set-Enable Register in the ARMv6-M ARM
ICER Interrupt Clear-Enable Register in the ARMv6-M ARM
ISPR Interrupt Set-Pending Register in the ARMv6-M ARM
ICPR Interrupt Clear-Pending Register in the ARMv6-M ARM
IPR0-IPR7 Interrupt Priority Registers in the ARMv6-M ARM