ARM Cortex-M0 User Manual

Programmers Model
3-4 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
3.3 Instruction set summary
The processor implements the ARMv6-M Thumb instruction set, including a number
of 32-bit instructions that use Thumb-2 technology. The ARMv6-M instruction set
comprises:
• all of the 16-bit Thumb instructions from ARMv7-M excluding
CBZ , CBNZ and IT
• the 32-bit Thumb instructions BL , DMB , DSB , ISB , MRS and MSR .
Table 3-1 shows the Cortex-M0 instructions and their cycle counts. The cycle counts
are based on a system with zero wait-states.
Table 3-1 Cortex-M0 instruction summary
Operation Description Assembler Cycles
Move 8-bit immediate
MOVS Rd , #<imm> 1
Lo to Lo
MOVS Rd , Rm 1
Any to Any
MOV Rd , Rm 1
Any to PC
MOV PC , Rm 3
Add 3-bit immediate
ADDS Rd , Rn , #<imm> 1
All registers Lo
ADDS Rd , Rn , Rm 1
Any to Any
ADD Rd , Rd , Rm 1
Any to PC
ADD PC , PC , Rm 3
8-bit immediate
ADDS Rd , Rd , #<imm> 1
With carry
ADCS Rd , Rd , Rm 1
Immediate to SP
ADD SP , SP, #<imm> 1
Form address from SP
ADD Rd , SP , #<imm> 1
Form address from PC
ADR Rd , <label> 1
Subtract Lo and Lo
SUBS Rd , Rn , Rm 1
3-bit immediate
SUBS Rd , Rn , #<imm> 1
8-bit immediate
SUBS Rd , Rd , #<imm> 1
With carry
SBCS Rd , Rd , Rm 1
Immediate from SP
SUB SP , SP , #<imm> 1

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent