ARM Cortex-M0 User Manual

Programmers Model
ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 3-5
ID112415 Non-Confidential
Subtract Negate RSBS Rd , Rn , #0 1
Multiply Multiply
MULS Rd , Rm , Rd
1 or 32
a
Compare Compare CMP Rn , Rm 1
Negative
CMN Rn , Rm 1
Immediate
CMP Rn , #<imm> 1
Logical AND
ANDS Rd , Rd , Rm 1
Exclusive OR
EORS Rd , Rd , Rm 1
OR
ORRS Rd , Rd , Rm 1
Bit clear
BICS Rd , Rd , Rm 1
Move NOT
MVNS Rd , Rm 1
AND test
TST Rn , Rm 1
Shift Logical shift left by immediate
LSLS Rd , Rm , #<shift> 1
Logical shift left by register
LSLS Rd , Rd , Rs 1
Logical shift right by immediate
LSRS Rd , Rm , #<shift> 1
Logical shift right by register
LSRS Rd , Rd , Rs 1
Arithmetic shift right
ASRS Rd , Rm , #<shift> 1
Arithmetic shift right by register
ASRS Rd , Rd , Rs 1
Rotate Rotate right by register
RORS Rd , Rd , Rs 1
Load Word, immediate offset
LDR Rd , [ Rn , #<imm> ]2
Halfword, immediate offset
LDRH Rd , [ Rn , #<imm> ]2
Byte, immediate offset
LDRB Rd , [ Rn , #<imm> ]2
Word, register offset
LDR Rd , [ Rn , Rm ]2
Halfword, register offset
LDRH Rd , [ Rn , Rm ]2
Signed halfword, register offset
LDRSH Rd , [ Rn , Rm ]2
Byte, register offset
LDRB Rd , [ Rn , Rm ]2
Table 3-1 Cortex-M0 instruction summary (continued)
Operation Description Assembler Cycles

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent