ARM Cortex-M0 User Manual

Debug
ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 6-5
ID112415 Non-Confidential
The SCS, DWT, and BPU ROM table entries point to the debug components at
addresses
0xE000E000 , 0xE0001000 and 0xE0002000 respectively. The value for each entry
is the offset of that component from the ROM table base address,
0xE00FF000 .
See the ARMv6-M ARM and the ARM CoreSight Components Technical Reference
Manual for more information about the ROM table ID and component registers, and
their addresses and access types.
6.1.2 System Control Space
If debug is implemented, the processor provides debug through registers in the SCS, see
Debug register summary on page 6-9.
SCS CoreSight identification
Table 6-3 shows the SCS CoreSight identification registers and values for debugger
detection. Final debugger identification of the Cortex-M0 processor is through the
CPUID register in the SCS, see CPUID Register on page 4-4.
See the ARMv6-M ARM and the ARM CoreSight Components Technical Reference
Manual for more information about the SCS CoreSight identification registers, and
their addresses and access types.
a. Reads as 0xFFF02002 if no watchpoints are implemented.
b. Reads as
0xFFF03002 if no breakpoints are implemented.
Table 6-3 SCS identification values
Register Value Description
Peripheral ID4
0x00000004 Component and Peripheral ID register formats in the ARMv6-M ARM
Peripheral ID0
0x00000008
Peripheral ID1 0x000000B0
Peripheral ID2 0x0000000B
Peripheral ID3 0x00000000
Component ID0 0x0000000D
Component ID1 0x000000E0
Component ID2 0x00000005
Component ID3 0x000000B1

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent