ARM Cortex-M0 User Manual

Debug
ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 6-7
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DWT Program Counter Sample Register
A processor that implements the data watchpoint unit also implements the ARMv6-M
optional DWT Program Counter Sample Register (DWT_PCSR). This register permits
a debugger to periodically sample the PC without halting the processor. This provides
coarse grained profiling. See the ARMv6-M ARM for more information.
The Cortex-M0 DWT_PCSR records both instructions that pass their condition codes
and those that fail.
6.1.4 Breakpoint unit
The Cortex-M0 BPU implementation provides between zero and four breakpoint
registers. A processor configured with zero breakpoints implements no breakpoint
functionality and the ROM table shows that no BPU is implemented.
BPU functionality
The processor breakpoints implement PC based breakpoint functionality, as described
in the ARMv6-M ARM.
BPU CoreSight identification
Table 6-5 shows the BPU identification registers and their values for debugger
detection.
Table 6-5 BPU identification registers
Register Value Description
Peripheral ID4
0x00000004 Component and Peripheral ID register formats in the ARMv6-M ARM
Peripheral ID0
0x0000000B
Peripheral ID1 0x000000B0
Peripheral ID2 0x0000000B
Peripheral ID3 0x00000000
Component ID0 0x0000000D
Component ID1 0x000000E0
Component ID2 0x00000005
Component ID3 0x000000B1

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent