ARM Cortex-M0 User Manual

Introduction
ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 1-5
ID112415 Non-Confidential
1.4 Configurable options
Table 1-1 shows the processor configurable options available at implementation time.
1.4.1 Configurable multiplier
The
MULS instruction provides a 32-bit x 32-bit multiply that yields the least-significant
32-bits. The processor can implement
MULS in one of two ways:
• as a fast single-cycle array
• as a 32-cycle iterative multiplier.
The iterative multiplier has no impact on interrupt response time because the processor
abandons multiply operations to take any pending interrupt.
Table 1-1 Processor configurable options
Feature Configurable option
Interrupts External interrupts 1, 2, 4, 8, 16, 24 or 32
Data endianness Little-endian or big-endian
SysTick timer Present or absent
Number of watchpoint comparators
a
a. Only when halting debug support is present.
0, 1, 2
Number of breakpoint comparators
a
0, 1, 2, 3, 4
Halting debug support Present or absent
Multiplier Fast or small

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent

Summary

Preface

About this book

Details the processor, revision status, intended audience, and book organization.

Conventions

Explains the typographical conventions used in the manual for clarity.

Additional reading

Lists other relevant ARM and third-party publications for further information.

Feedback

Provides contact information and guidelines for submitting feedback on the processor and manual.

Chapter 1 Introduction

1.1 About the processor

Describes the Cortex-M0 processor as a low gate count, energy-efficient processor for embedded applications.

1.2 Features

Lists key features and benefits of the Cortex-M0 processor, including instruction set and power control.

1.3 Interfaces

Details the external interfaces of the processor, such as AHB-Lite and Debug Access Port (DAP).

1.4 Configurable options

Explains the processor's configurable options available at implementation time, like interrupts and multiplier.

1.5 Product documentation, design flow and architecture

Discusses the relationship between processor books, design flow, and architectural standards.

1.6 Product revisions

Describes the differences in functionality between product revisions of the Cortex-M0.

Chapter 2 Functional Description

2.1 About the functions

Provides an overview of the Cortex-M0 processor's functional blocks and implemented features.

2.2 Interfaces

Describes the external interface functions, including AHB-Lite and Debug Access Port (DAP).

Chapter 3 Programmers Model

3.1 About the programmers model

Introduces the application-level programmers model and its relation to the ARMv6-M ARM.

3.2 Modes of operation and execution

Explains the modes of operation and execution for the Cortex-M0 processor.

3.3 Instruction set summary

Summarizes the ARMv6-M Thumb instruction set and their cycle counts.

3.4 Memory model

Describes the processor's memory map, which is ARMv6-M architecture compliant.

3.5 Processor core registers summary

Summarizes the Cortex-M0 processor core registers, including their names and descriptions.

3.6 Exceptions

Describes the exception model of the processor and exception handling mechanisms.

Chapter 4 System Control

4.1 About system control

Describes system control registers that configure various system control functions.

4.2 System control register summary

Summarizes the system control registers, their names, reset values, and descriptions.

Chapter 5 Nested Vectored Interrupt Controller

5.1 About the NVIC

Explains the functionality of the Nested Vectored Interrupt Controller (NVIC) and its features.

5.2 NVIC register summary

Summarizes the NVIC registers, their names, and descriptions.

Chapter 6 Debug

6.1 About debug

Provides an overview of the debug system, including basic functionality and optional features.

6.2 Debug register summary

Summarizes the debug registers, BPU registers, and DWT registers.

Appendix A Revisions

Glossary