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ARM Cortex-M0 User Manual

ARM Cortex-M0
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ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 6-1
ID112415 Non-Confidential
Chapter 6
Debug
This chapter summarizes the debug system. It contains the following sections:
About debug on page 6-2
Debug register summary on page 6-9.

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ARM Cortex-M0 Specifications

General IconGeneral
ArchitectureARMv6-M
Data Bus Width32-bit
Clock SpeedUp to 50 MHz
InterruptsNested Vectored Interrupt Controller (NVIC)
Number of Cores1
Memory ProtectionOptional Memory Protection Unit (MPU)
Interrupt ControllerNested Vectored Interrupt Controller (NVIC)
Pipeline3-stage
Max Clock Speed50 MHz
Instruction SetThumb
Power ConsumptionLow power design
DebugSerial Wire Debug (SWD)
Die SizeImplementation dependent

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