ARM Cortex-M0 User Manual

ARM DDI 0432C Copyright © 2009 ARM Limited. All rights reserved. 5-1
ID112415 Non-Confidential
Chapter 5
Nested Vectored Interrupt Controller
This chapter summarizes the Nested Vectored Interrupt Controller (NVIC). It contains
the following sections:
• About the NVIC on page 5-2
• NVIC register summary on page 5-3.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent