ARM Cortex-M0 User Manual

ii Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
Cortex-M0
Technical Reference Manual
Copyright © 2009 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this book.
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The information in this document is final, that is for a developed product.
Change history
Date Issue Confidentiality Change
19 March 2009 A Non-Confidential, Restricted Access First release for r0p0
27 July 2009 B Non-Confidential, Restricted Access Second release for r0p0
30 November 2009 C Non-Confidential Third release for r0p0

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent