C11.39 Single-Shot Comparator Control Register 0
The TRCSSCCR0 characteristics are:
Purpose
Controls the single-shot comparator.
Usage constraints
Accepts writes only when the trace unit is disabled.
Configurations
Available in all configurations.
Attributes
See C11.1 ETM register summary on page C11-733.
RES0RES0
31 20 19 16 15 8 7 0
ARC RES0 SAC
24 2325
RST
Figure C11-38 TRCSSCCR0 bit assignments
[31:25]
Reserved, RES0.
RST, [24]
Enables the single-shot comparator resource to be reset when it occurs, to enable another
comparator match to be detected:
1 Reset enabled. Multiple matches can occur.
[23:20]
Reserved, RES0.
ARC, [19:16]
Selects one or more address range comparators for single-shot control.
One bit is provided for each implemented address range comparator.
[15:8]
Reserved, RES0.
SAC, [7:0]
Selects one or more single address comparators for single-shot control.
One bit is provided for each implemented single address comparator.
The TRCSSCCR0 can be accessed through the external debug interface, offset 0x280.
C11 ETM registers
C11.39 Single-Shot Comparator Control Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C11-785
Non-Confidential
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