B1.38 Configuration Base Address Register
The CBAR characteristics are:
Purpose
Holds the physical base address of the memory-mapped GIC CPU interface registers.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Configurations
The CBAR is Common to the Secure and Non-secure states.
Attributes
CBAR is a 32-bit register.
31
8 7 0
RES0PERIPHBASE[31:18] PERIPHBASE[39:32]
1718
Figure B1-2 CBAR bit assignments
PERIPHBASE[31:18], [31:18]
If the processor is implemented with the GIC CPU interface, the input PERIPHBASE[31:18]
determines the reset value. If the GIC CPU interface is not implemented, this field is RAZ.
[17:8]
Reserved, RES0.
PERIPHBASE[39:32], [7:0]
If the processor is implemented with the GIC CPU interface, the input PERIPHBASE[39:32]
determines the reset value. If the GIC CPU interface is not implemented, this field is RAZ.
To access the CBAR:
MRC p15, 1, <Rt>, c15, c3, 0; Read CBAR into Rt
Register access is encoded as follows:
Table B1-31 CBAR access encoding
coproc opc1 CRn CRm opc2
1111 001 1111 0011 000
B1 AArch32 system registers
B1.38 Configuration Base Address Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-200
Non-Confidential
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