ARM Cortex-A35 User Manual

B2.31 Architectural Feature Access Control Register, EL1
The CPACR_EL1 characteristics are:
Purpose
Controls access to trace functionality and access to registers associated with Advanced SIMD
and floating-point execution.
CPACR_EL1 is part of the Other system registers functional group.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Configurations
CPACR_EL1 is architecturally mapped to AArch32 register CPACR. See B1.41 Architectural
Feature Access Control Register on page B1-206.
Attributes
CPACR_EL1 is a 32-bit register.
31 0
RES0
TTA
RES0
FPEN
1928 27 20212229
RES0
Figure B2-6 CPACR_EL1 bit assignments
[31:29]
Reserved, RES0.
TTA, [28]
Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1.
This bit is RES0.
[27:22]
Reserved, RES0.
FPEN, [21:20]
Traps instructions that access registers associated with Advanced SIMD and floating-point
execution to trap to EL1 when executed from EL0 or EL1. The possible values are:
0bX0 Trap any instruction in EL0 or EL1 that uses registers associated with Advanced SIMD
and floating-point execution. The reset value is 0b00.
0b01 Trap any instruction in EL0 that uses registers associated with Advanced SIMD and
floating-point execution. Instructions in EL1 are not trapped.
0b11 No instructions are trapped.
This field is RES0 if Advanced SIMD and floating-point are not implemented.
[19:0]
Reserved, RES0.
B2 AArch64 system registers
B2.31 Architectural Feature Access Control Register, EL1
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B2-402
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English