ARM Cortex-A35 User Manual

B1.61 Hyp Configuration Register
The HCR characteristics are:
Purpose
Provides configuration controls for virtualization, including defining whether various Non-
secure operations are trapped to Hyp mode.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW -
Configurations
HCR is architecturally mapped to AArch64 register HCR_EL2[31:0]. See B2.48 Hypervisor
Configuration Register, EL2 on page B2-433.
Attributes
HCR is a 32-bit register.
31 030 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TRVM
RES0 VM
SWIO
PTW
FMO
IMO
AMO
VF
VI
VA
FB
BSU
DC
TWI
TWE
TID0
HCD
RES0
TGE
TVM
TTLB
TPU
TSW
TAC
TIDCP
TSC
TID3
TID2
TID1
TPC
Figure B1-17 HCR bit assignments
[31]
Reserved, RES0.
TRVM, [30]
Trap Read of Virtual Memory controls.
When 1, this causes Reads to the EL1 virtual memory control registers from EL1 to be trapped
to EL2. This covers the following registers:
SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR,
PRRR/MAIR0, NMRR/MAIR1, AMAIR0, AMAIR1, and CONTEXTIDR.
The reset value is 0.
B1 AArch32 system registers
B1.61 Hyp Configuration Register
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B1-240
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English