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ARM Cortex-A35 User Manual

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HCD, [29]
Hyp Call Disable. The HCD value is:
0 HVC is enabled at EL1 or EL2.
1 HVC is UNDEFINED at all exception levels.
[28]
Reserved, RES0.
TGE, [27]
Trap General Exceptions. If this bit is set, and SCR_EL3.NS is set, then:
All exceptions that would be routed to EL1 are routed to EL2.
The SCTLR.M bit is treated as 0 regardless of its actual state, other than for the purpose of
reading the bit.
The HCR.FMO, IMO, and AMO bits are treated as 1 regardless of their actual state, other
than for the purpose of reading the bits.
All virtual interrupts are disabled.
Any implementation defined mechanisms for signaling virtual interrupts are disabled.
An exception return to EL1 is treated as an illegal exception return.
Additionally, if HCR.TGE is 1, the HDCR.{TDRA,TDOSA,TDA} bits are ignored and the
processor behaves as if they are set to 1, other than for the value read back from HDCR.
The reset value is 0.
TVM, [26]
Trap Virtual Memory controls. When 1, this causes Writes to the EL1 virtual memory control
registers from EL1 to be trapped to EL2. This covers the following registers:
SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR,
PRRR/MAIR0, NMRR/MAIR1, AMAIR0, AMAIR1, and CONTEXTIDR.
The reset value is 0.
TTLB, [25]
Trap TLB maintenance instructions. When 1, this causes TLB maintenance instructions
executed from EL1 that are not UNDEFINED to be trapped to EL2. This covers the following
instructions:
TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIALL, TLBIMVA, TLBIASID, TLBIMVAA,
TLBIMVALIS, TLBIMVAALIS, TLBIMVAL, and TLBIMVAAL.
The reset value is 0.
TPU, [24]
Trap Cache maintenance instructions to Point of Unification. When 1, this causes Cache
maintenance instructions to the point of unification executed from EL1 or EL0 that are not
UNDEFINED to be trapped to EL2. This covers the following instructions:
ICIMVAU, ICIALLU, ICIALLUIS, and DCCMVAU.
The reset value is 0.
B1 AArch32 system registers
B1.61 Hyp Configuration Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-241
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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