TPC, [23]
Trap Data/Unified Cache maintenance operations to Point of Coherency. When 1, this causes
Data or Unified Cache maintenance instructions by address to the point of coherency executed
from EL1 or EL0 that are not UNDEFINED to be trapped to EL2. This covers the following
instructions:
DCIMVAC, DCCIMVAC, and DCCMVAC.
The reset value is 0.
TSW, [22]
Trap Data/Unified Cache maintenance operations by Set/Way. When 1, this causes Data or
Unified Cache maintenance instructions by set/way executed from EL1 that are not UNDEFINED to
be trapped to EL2. This covers the following instructions:
DCISW, DCCSW, and DCCISW.
The reset value is 0.
TAC, [21]
Trap ACTLR accesses. When this bit is set to 1, any valid Non-secure access to the ACTLR is
trapped to Hyp mode.
The reset value is 0.
TIDCP, [20]
Trap Implementation Dependent functionality. When 1, this causes accesses to all CP15 MCR
and MRC instructions executed from EL1, to be trapped to EL2 as follows:
• CRn is 9, Opcode1 is 0 to 7, CRm is c0, c1, c2, c5, c6, c7, c8, opcode2 is 0 to 7.
• CRn is 10, Opcode1 is 0 to 7, CRm is c0, c1, c4, c8}, opcode2 is 0 to 7.
• CRn is 11, Opcode1 is 0 to 7, CRm is c0 to c8, or c15, opcode2 is 0 to 7.
Accesses from EL0 are UNDEFINED.
Resets to 0.
TSC, [19]
Trap SMC instruction. When this bit is set to 1, any attempt from a Non-secure EL1 state to
execute an SMC instruction, that passes its condition check if it is conditional, is trapped to Hyp
mode.
The reset value is 0.
TID3, [18]
Trap ID Group 3. When 1, this causes reads to the following registers executed from EL1 to be
trapped to EL2:
ID_PFR0, ID_PFR1, ID_DFR0, ID_AFR0, ID_MMFR0, ID_MMFR1, ID_MMFR2,
ID_MMFR3, ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, ID_ISAR5, MVFR0,
MVFR1, and MVFR2. Also MRC instructions to any of the following encodings:
• CP15, OPC1 is 0, CRn is 0, CRm is c3, c4, c5, c6, or c7, and Opc2 is 0 or 1.
• CP15, Opc1 is 0, CRn is 0, CRm is c3, and Opc2 is 2.
• CP15, Opc1 is 0, CRn is 0, CRm is 5, and Opc2 is 4 or 5.
The reset value is 0.
B1 AArch32 system registers
B1.61 Hyp Configuration Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-242
Non-Confidential
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