ARM Cortex-A35 User Manual

B1.32 Auxiliary Control Register
The ACTLR characteristics are:
Purpose
Controls write access to IMPLEMENTATION DEFINED registers in EL2, such as CPUACTLR,
CPUECTLR, L2CTLR, L2ECTLR, and L2ACTLR.
Usage constraints
This register is accessible as follows:
EL0
NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
Configurations
The processor does not implement the ACTLR (NS) register. This register is always RES0. It is
mapped to AArch64 register ACTLR_EL1. See B2.19 Auxiliary Control Register, EL1
on page B2-386.
ACTLR (S) is mapped to AArch64 register ACTLR_EL3. See B2.21 Auxiliary Control Register,
EL3 on page B2-389.
Attributes
ACTLR is a 32-bit register.
RES0
31 7 6 5 1 0
RES0
4 3 2
L2ACTLR access control
L2ECTLR access control
L2CTLR access control
CPUECTLR access control
CPUACTLR access control
Figure B1-1 ACTLR bit assignments
[31:7]
Reserved, RES0.
L2ACTLR access control, [6]
L2ACTLR write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
1 The register is write accessible from EL2.
L2ECTLR access control, [5]
L2ECTLR write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
1 The register is write accessible from EL2.
L2CTLR access control, [4]
L2CTLR write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
B1 AArch32 system registers
B1.32 Auxiliary Control Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English