1 The register is write accessible from EL2.
[3:2]
Reserved, RES0.
CPUECTLR access control, [1]
CPUECTLR write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
1 The register is write accessible from EL2.
CPUACTLR access control, [0]
CPUACTLR write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
1 The register is write accessible from EL2.
To access the ACTLR:
MRC p15, 0, <Rt>, c1, c0, 1 ; Read ACTLR into Rt
MCR p15, 0, <Rt>, c1, c0, 1 ; Write Rt to ACTLR
Register access is encoded as follows:
Table B1-30 ACTLR access encoding
coproc opc1 CRn CRm opc2
1111 000 0001 0000 001
B1 AArch32 system registers
B1.32 Auxiliary Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-194
Non-Confidential
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