ARM Cortex-A35 User Manual

B1.31 AArch32 Implementation defined registers
IMPLEMENTATION DEFINED registers provide test features and any required configuration options specific to
the Cortex‑A35 processor.
The following table shows the 32-bit wide implementation defined registers.
Table B1-29 Memory access registers
Name CRn Op1 CRm Op2 Reset Width Description
L2CTLR c9 1 c0 2
-
32-bit
B1.92 L2 Control Register on page B1-303
The reset value depends on the processor
configuration.
L2ECTLR 3
0x00000000
32-bit B1.93 L2 Extended Control Register on page B1-305
L2ACTLR c15 1 c0 0
0x80000000
32-bit
B1.91 L2 Auxiliary Control Register on page B1-301
This is the reset value for an ACE interface. For an
AXI interface the reset value is 0x80000008. For a
CHI interface the reset value is 0x80004008.
CBAR c3 0 - 32-bit
B1.38 Configuration Base Address Register
on page B1-200
The reset value depends on the processor
configuration.
CDBGDR0 3 c0 0 UNK 32-bit
Data Register 0, see C5.1 About direct access to
internal memory on page C5-608 for information on
how these registers are used.
CDBGDR1 1 UNK 32-bit Data Register 1, see C5.1 About direct access to
internal memory on page C5-608
CDBGDR2 2 UNK 32-bit Data Register 2, see C5.1 About direct access to
internal memory on page C5-608
CDBGDR3 3 UNK 32-bit Data Register 3, see C5.1 About direct access to
internal memory on page C5-608.
CDBGDCT c2 0 UNK 32-bit Data Cache Tag Read Operation Register, see
C5.1 About direct access to internal memory
on page C5-608
CDBGICT 1 UNK 32-bit Instruction Cache Tag Read Operation Register, see
C5.1 About direct access to internal memory
on page C5-608
CDBGDCD c4 0 UNK 32-bit Data Cache Data Read Operation Register, see
C5.1 About direct access to internal memory
on page C5-608
CDBGICD 1 UNK 32-bit Instruction Cache Data Read Operation Register, see
C5.1 About direct access to internal memory
on page C5-608
CDBGTD 2 UNK 32-bit TLB Data Read Operation Register, see C5.1 About
direct access to internal memory on page C5-608
B1 AArch32 system registers
B1.31 AArch32 Implementation defined registers
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English