ARM Cortex-A35 User Manual

A.10 Broadcast signals for the memory interface
The processor has broadcast signals for the memory interface. These signals are only sampled at
processor reset.
The signals in the following table only exist if the processor is configured to have an ACE or CHI
memory interface.
Table A-17 Broadcast signals
Signal Direction Description
BROADCASTCACHEMAINT Input
Enable broadcasting of cache maintenance operations to downstream caches:
0
Cache maintenance operations are not broadcast to downstream caches.
1
Cache maintenance operations are broadcast to downstream caches.
BROADCASTINNER Input
Enable broadcasting of Inner Shareable transactions:
0
Inner Shareable transactions are not broadcast externally.
1
Inner Shareable transactions are broadcast externally.
If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTER
HIGH.
BROADCASTOUTER Input
Enable broadcasting of outer shareable transactions:
0
Outer Shareable transactions are not broadcast externally.
1
Outer Shareable transactions are broadcast externally.
A Signal Descriptions
A.10 Broadcast signals for the memory interface
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English