ARM Cortex-A35 User Manual

B1.122 Virtualization Translation Control Register
The VTCR characteristics are:
Purpose
Controls the translation table walks required for the stage 2 translation of memory accesses from
Non-secure modes other than Hyp mode, and holds cacheability and shareability information for
the accesses.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Used in conjunction with VTTBR, that defines the translation table base address for the
translations.
Configurations
VTCR is architecturally mapped to AArch64 register VTCR_EL2. See B2.105 Virtualization
Translation Control Register, EL2 on page B2-556.
This register is accessible only at EL2 or EL3.
Attributes
VTCR is a 32-bit register.
31
0
RES0
567891011121314
ORGN0
IRGN0
SH0 SL0 T0SZS
RES0
34
RES1
30
Figure B1-70 VTCR bit assignments
[31]
Reserved, RES1.
[30:14]
Reserved, RES0.
SH0, [13:12]
Shareability attribute for memory associated with translation table walks using TTBR0.
0b00 Non-shareable.
0b01 Reserved.
0b10 Outer Shareable.
0b11 Inner Shareable.
ORGN0, [11:10]
Outer cacheability attribute for memory associated with translation table walks using TTBR0.
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
B1 AArch32 system registers
B1.122 Virtualization Translation Control Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English