0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
IRGN0, [9:8]
Inner cacheability attribute for memory associated with translation table walks using TTBR0.
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
SL0, [7:6]
Starting level for translation table walks using VTTBR:
0b00 Start at second level.
0b01 Start at first level.
[5]
Reserved, RES0.
S, [4]
Sign extension bit. This bit must be programmed to the value of T0SZ[3]. If it is not, then the
stage 2 T0SZ value is treated as an UNKNOWN value within the legal range that can be
programmed.
T0SZ, [3:0]
The size offset of the memory region addressed by TTBR0. The region size is 2
32-T0SZ
bytes.
To access the VTCR:
MRC p15, 4, <Rt>, c2, c1, 2; Read VTCR into Rt
MCR p15, 4, <Rt>, c2, c1, 2; Write Rt to VTCR
Register access is encoded as follows:
Table B1-101 VTCR access encoding
coproc opc1 CRn CRm opc2
1111 100 0010 0001 010
B1 AArch32 system registers
B1.122 Virtualization Translation Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-358
Non-Confidential
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