B2.77 Memory Attribute Indirection Register, EL1
The MAIR_EL1 characteristics are:
Purpose
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a
Long-descriptor format translation table entry for stage 1 translations at EL1.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
MAIR_EL1 is permitted to be cached in a TLB.
Configurations
MAIR_EL1[31:0] is architecturally mapped to AArch32 register:
• PRRR (NS) when TTBCR.EAE is 0. See B1.101 Primary Region Remap Register
on page B1-322.
• MAIR0 (NS) when TTBCR.EAE is 1. See B1.95 Memory Attribute Indirection Registers 0
and 1 on page B1-310.
MAIR_EL1[63:32] is architecturally mapped to AArch32 register:
• NMRR (NS) when TTBCR.EAE is 0. See B1.99 Normal Memory Remap Register
on page B1-319.
• MAIR1(NS) when TTBCR.EAE is 1. See B1.95 Memory Attribute Indirection Registers 0
and 1 on page B1-310.
Attributes
MAIR_EL1 is a 64-bit register.
Attr7
063
Attr5Attr6 Attr4 Attr0Attr1Attr2Attr3
8162432404856 7152331394755
Figure B2-49 MAIR_EL1 bit assignments
Attr<n> is the memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format
translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.
Table B2-68 Attr<n>[7:4] bit assignments
Bits Meaning
0b0000
Device memory. See Table B2-69 Attr<n>[3:0] bit assignments on page B2-497
0b00RW, RW not 00 Normal Memory, Outer Write-through transient. The transient hint is ignored.
0b0100
Normal Memory, Outer Non-Cacheable.
0b01RW, RW not 00 Normal Memory, Outer Write-back transient. The transient hint is ignored.
0b10RW
Normal Memory, Outer Write-through non-transient.
0b11RW
Normal Memory, Outer Write-back non-transient.
B2 AArch64 system registers
B2.77 Memory Attribute Indirection Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-496
Non-Confidential
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