A5.2 Coherency between data caches with the MOESI protocol
The processor uses the MOESI protocol to maintain data cache coherency between multiple cores. The
DCU stores the MOESI state of the cache line in the tag and dirty RAMs.
MOESI describes the state in which a shareable line can be in an L1 data cache.
Table A5-1 MOESI and AMBA mapping
MOESI AMBA Description
Modified UniqueDirty The line is in only this cache and is dirty.
Owned SharedDirty The line is possibly in more than one cache and is dirty.
Exclusive UniqueClean The line is in only this cache and is clean.
Shared SharedClean The line is possibly in more than one cache and is clean.
Invalid Invalid The line is not in this cache.
Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. You must set the SMPEN bit
before enabling the data cache. If you do not, then the cache is not coherent with other cores and data
corruption could occur.
Related information
A5.6 About read allocate mode on page A5-83
B1.43 CPU Extended Control Register on page B1-212
C5.3 Encoding for tag and data in the L1 data cache on page C5-610
A5 Cache Behavior and Cache Protection
A5.2 Coherency between data caches with the MOESI protocol
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