B1.85 Processor Feature Register 1
The ID_PFR1 characteristics are:
Purpose
Provides information about the programmers model and architecture extensions supported by
the processor.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_PFR0.
Configurations
ID_PFR1 is architecturally mapped to AArch64 register ID_PFR1_EL1. See B2.68 AArch32
Processor Feature Register 1, EL1 on page B2-477.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_PFR1 is a 32-bit register.
31
12 11 8 7 0
GIC CPU
4 316 15
Virtualization
20 1923242728
Reserved GenTimer MProgMod Security ProgMod
Figure B1-40 ID_PFR1 bit assignments
GIC CPU, [31:28]
GIC CPU support:
0x0 GIC CPU interface is disabled, GICCDISABLE is HIGH, or not implemented.
0x1 GIC CPU interface is implemented and enabled, GICCDISABLE is LOW.
[27:20]
Reserved, RAZ.
GenTimer, [19:16]
Generic Timer support:
0x1 Generic Timer implemented.
Virtualization, [15:12]
Indicates support for Virtualization:
0x1 Virtualization implemented.
MProgMod, [11:8]
M profile programmers model support:
0x0 Not supported.
Security, [7:4]
B1 AArch32 system registers
B1.85 Processor Feature Register 1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-291
Non-Confidential
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