C10.3 Performance Monitors Common Event Identification Register 0
The PMCEID0 characteristics are:
Purpose
Defines which common architectural and common microarchitectural feature events are
implemented.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config Config RO RO RO RO RO
This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.
Configurations
The PMCEID0 is architecturally mapped to:
• The AArch64 register PMCEID0_EL0. See C10.7 Performance Monitors Common Event
Identification Register 0, EL0 on page C10-707.
• The external register PMCEID0_EL0.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
PMCEID0 is a 32-bit register.
CE
31
08 716 15 12346111230 29 28 27 26 25 24 23 22 21 20 19 18 17 1314 910 5
Figure C10-2 PMCEID0 bit assignments
CE[31:0], [31:0]
Common architectural and microarchitectural feature events that can be counted by the PMU
event counters.
The following table shows the PMCEID0 bit assignments with event implemented or not
implemented when the associated bit is set to 1 or 0. See the Arm
®
Architecture Reference
Manual Armv8, for Armv8-A architecture profile for more information about these events.
Table C10-2 PMU events
Bit Event number Event mnemonic Description
[31]
0x1F
L1D_CACHE_ALLOCATE
L1 Data cache allocate:
0
This event is not implemented.
[30]
0x1E
CHAIN
Chain. For odd-numbered counters, counts once for each overflow of the
preceding even-numbered counter. For even-numbered counters, does not
count:
1
This event is implemented.
C10 PMU registers
C10.3 Performance Monitors Common Event Identification Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-695
Non-Confidential
To Next Page
Loading...
Need help?
General
