0 All counters, including PMCCNTR, are disabled. This is the reset value.
1 All counters are enabled.
This bit is RW.
In Non-secure EL0 and EL1, this bit does not affect the operation of event counters that
HDCR_EL2.HPMN reserves for EL2 use.
On Warm reset, the field resets to 0.
To access the PMCR:
MRC p15,0,<Rt>,c9,c12,0 ; Read PMCR into Rt
MCR p15,0,<Rt>,c9,c12,0 ; Write Rt to PMCR
The PMCR can be accessed through the external debug interface, offset 0xE04.
C10 PMU registers
C10.2 Performance Monitors Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-694
Non-Confidential
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