Long cycle count enable. Determines which PMCCNTR bit generates an overflow recorded in
PMOVSR[31]. The possible values are:
0 Overflow on increment that changes PMCCNTR[31] from 1 to 0.
1 Overflow on increment that changes PMCCNTR[63] from 1 to 0.
DP, [5]
Disable cycle counter, PMCCNTR when event counting is prohibited:
0 Cycle counter operates regardless of the non-invasive debug authentication
settings. This is the reset value.
1 Cycle counter is disabled if non-invasive debug is not permitted and enabled.
This bit is read/write.
X, [4]
Export enable. This bit permits events to be exported to another debug device, such as a trace
macrocell, over an event bus:
0 Export of events is disabled. This is the reset value.
1 Export of events is enabled.
This bit is read/write and does not affect the generation of Performance Monitors interrupts on
the nPMUIRQ pin.
D, [3]
Clock divider:
0 When enabled, PMCCNTR counts every clock cycle. This is the reset value.
1 When enabled, PMCCNTR counts every 64 clock cycles.
This bit is read/write.
C, [2]
Clock counter reset. This bit is WO. The effects of writing to this bit are:
0 No action. This is the reset value.
1 Reset PMCCNTR_EL0 to 0.
This bit is always RAZ.
Resetting PMCCNTR does not clear the PMCCNTR overflow bit to 0. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
P, [1]
Event counter reset. This bit is WO. The effects of writing to this bit are:
0 No action. This is the reset value.
1 Reset all event counters, not including PMCCNTR, to zero.
This bit is always RAZ.
In Non-secure EL0 and EL1, a write of 1 to this bit does not reset event counters that
HDCR.HPMN reserves for EL2 use.
In EL2 and EL3, a write of 1 to this bit resets all the event counters.
Resetting the event counters does not clear any overflow bits to 0.
E, [0]
Enable. The possible values of this bit are:
C10 PMU registers
C10.2 Performance Monitors Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-693
Non-Confidential
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