ARM Cortex-A35 User Manual

B2.53 AArch64 Memory Model Feature Register 0, EL1
The ID_AA64MMFR0_EL1 characteristics are:
Purpose
Provides information about the implemented memory model and memory management support
in the AArch64 Execution state.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Attributes
ID_AA64MMFR0_EL1 is a 64-bit register.
63 0
RES0
4 38 712 1116 15
BigEnd ASIDBits
20 19
SNSMemTGran16 PARange
24 23
TGran64
28 27
TGran4
32 31
BigEndEL0
Figure B2-27 ID_AA64MMFR0_EL1 bit assignments
[63:32]
Reserved, RES0.
TGran4, [31:28]
Support for 4KB memory translation granule size:
0x0 Indicates that the 4KB granule is supported.
TGran64, [27:24]
Support for 64KB memory translation granule size:
0x0 Indicates that the 64KB granule is supported.
TGran16, [23:20]
Support for 16KB memory translation granule size:
0x1 Indicates that the 16KB granule is supported.
BigEndEL0, [19:16]
Mixed-endian support only at EL0.
RES0
SNSMem, [15:12]
Secure versus Non-secure Memory distinction:
0b0001 Supports a distinction between Secure and Non-secure Memory.
BigEnd, [11:8]
Mixed-endian configuration support:
0b0001 Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits are RW.
B2 AArch64 system registers
B2.53 AArch64 Memory Model Feature Register 0, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-448
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English