About this book
This Technical Reference Manual is for the Cortex
®
‑A35 processor. It provides reference documentation
and contains programming details for registers. It also describes the memory system, the caches, the
interrupts, and the debug features.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2,
where:
rm Identifies the major revision of the product, for example, r1.
pn Identifies the minor revision or modification status of the product, for example, p2.
Intended audience
This manual is written for system designers, system integrators, and programmers who are designing or
programming a System-on-Chip (SoC) that uses the Cortex
®
‑A35 processor.
Using this book
This book is organized into the following chapters:
Part A Functional Description
This part describes the main functionality of the Cortex‑A35 processor.
Chapter A1 Introduction
This chapter provides an overview of the Cortex‑A35 processor and its features.
Chapter A2 Technical Overview
This chapter describes the structure of the Cortex‑A35 processor.
Chapter A3 Clocks, Resets, and Input Synchronization
This chapter describes the clocks of the Cortex‑A35 processor. It also describes the reset options.
Chapter A4 Power Management
This chapter describes the power domains and the power modes in the Cortex‑A35 processor.
Chapter A5 Cache Behavior and Cache Protection
This chapter describes the CPU and SCU cache protection features of the Cortex‑A35 processor.
Chapter A6 L1 Memory System
This chapter describes the L1 instruction cache and data cache.
Chapter A7 L2 Memory System
This chapter describes the L2 memory system and the Snoop Control Unit (SCU) that is tightly
integrated with it.
Chapter A8 AXI Master Interface
This chapter describes the AXI master memory interface.
Chapter A9 ACE Master Interface
This chapter describes the ACE master interface.
Chapter A10 CHI Master Interface
This chapter describes the CHI master memory interface.
Chapter A11 ACP Slave Interface
This chapter describes the ACP slave interface.
Chapter A12 GIC CPU Interface
This chapter describes the Generic Interrupt Controller (GIC) CPU interface of the processor.
Part B Register Descriptions
This part describes the non-debug registers of the Cortex‑A35 processor.
Preface
Product revision status
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
20
Non-Confidential
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