B1.22 AArch32 Fault handling registers
The following table shows the Fault handling registers in the AArch32 Execution state.
Table B1-21 Fault handling registers
Name CRn Op1 CRm Op2 Reset Description
DFSR c5 0 c0 0 UNK B1.49 Data Fault Status Register on page B1-223
IFSR 1 UNK B1.87 Instruction Fault Status Register on page B1-294
ADFSR c1 0
0x00000000
B1.33 Auxiliary Data Fault Status Register on page B1-195
AIFSR 1
0x00000000
B1.35 Auxiliary Instruction Fault Status Register on page B1-197
DFAR c6 0 c0 0 UNK
Data Fault Address Register, see the Arm
®
Architecture Reference Manual
Armv8, for Armv8-A architecture profile
IFAR 2 UNK
Instruction Fault Address Register, see the Arm
®
Architecture Reference Manual
Armv8, for Armv8-A architecture profile
The Virtualization registers include additional fault handling registers. See B1.28 AArch32 Virtualization
registers on page B1-186 for more information.
B1 AArch32 system registers
B1.22 AArch32 Fault handling registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-179
Non-Confidential
To Next Page
Loading...
