B1.66 Hyp IPA Fault Address Register
The HPFAR characteristics are:
Purpose
Holds the faulting IPA for some aborts on a stage 2 translation taken to Hyp mode.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Execution in any Non-secure mode other than Hyp mode makes HPFAR UNKNOWN.
Configurations
HPFAR is architecturally mapped to AArch64 register HPFAR_EL2[31:0]. See
B2.49 Hypervisor IPA Fault Address Register, EL2 on page B2-440.
Attributes
HPFAR is a 32-bit register.
31
0
FIPA[39:12]
4 3
RES0
Figure B1-22 HPFAR bit assignments
FIPA[39:12], [31:4]
Bits [39:12] of the faulting intermediate physical address
[3:0]
Reserved, RES0
To access the HPFAR:
MRC p15, 4, <Rt>, c6, c0, 4 ; Read HPFAR into Rt
MCR p15, 4, <Rt>, c6, c0, 4 ; Write Rt to HPFAR
Register access is encoded as follows:
Table B1-51 HPFAR access encoding
coproc opc1 CRn CRm opc2
1111 100 0110 0000 100
B1 AArch32 system registers
B1.66 Hyp IPA Fault Address Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-253
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