ARM Cortex-A35 User Manual

B1.105 System Control Register
The SCTLR characteristics are:
Purpose
Provides the top level control of the system, including its memory system.
Usage constraints
The SCTLR is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
Control bits in the SCTLR that are not applicable to a VMSA implementation read as the value
that most closely reflects that implementation, and ignore writes.
Some bits in the register are read-only. These bits relate to non-configurable features of an
implementation, and are provided for compatibility with previous versions of the architecture.
Configurations
SCTLR (NS) is architecturally mapped to AArch64 register SCTLR_EL1. See B2.90 System
Control Register, EL1 on page B2-525.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
If EL3 is using AArch32, write access to SCTLR(S) is disabled when the CP15SDISABLE2
signal is asserted HIGH.
Attributes
SCTLR is a 32-bit register.
31
30 29 28 27 26 25 24 14 13 12 11 3 2 1 0
MI
RES0
V C A
EE
TRE
AFE
TE
1821 20 19
UWXN
WXN
917 16 15
RES1
nTWE
RES0
nTWI
RES0
8 7 6 5 4
CP15BEN
THEE
ITD
SED
RES0
RES0
23 22
RES0
RES1
RES1
RES0
Figure B1-58 SCTLR bit assignments
[31]
Reserved, RES0.
TE, [30]
T32 Exception enable. This bit controls whether exceptions are taken in A32 or T32 state:
0 Exceptions, including reset, taken in A32 state.
1 Exceptions, including reset, taken in T32 state.
The input CFGTE defines the reset value of the TE bit.
AFE, [29]
B1 AArch32 system registers
B1.105 System Control Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English