ARM Cortex-A35 User Manual

B1.67 Hyp System Control Register
The HSCTLR characteristics are:
Purpose
Provides top level control of the system operation in Hyp mode. This register provides Hyp
mode control of features controlled by the Banked SCTLR bits, and shows the values of the
non-Banked SCTLR bits.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Configurations
HSCTLR is architecturally mapped to AArch64 register SCTLR_EL2. See B2.91 System
Control Register, EL2 on page B2-529.
Attributes
HSCTLR is a 32-bit register.
RES0RES0RES1RES0
M
31 30 29 26 25 24 22 21 20 19 18 13 12 11 7 6 3 2 1 0
TE RES1 EE FI I
RES1 C A
WXN
RES0 RES0
9
RES0
SED
8
ITD
RES1
5 4
CP15BEN
RES0
2728 23 17 16 15 14 10
RES1
RES1
RES0
Figure B1-23 HSCTLR bit assignments
[31]
Reserved, RES0.
TE, [30]
Thumb Exception enable. This bit controls whether exceptions taken in Hyp mode are taken in
A32 or T32 state:
0 Exceptions taken in A32 state.
1 Exceptions taken in T32 state.
[29:28]
Reserved, RES1.
[27:26]
Reserved, RES0.
EE, [25]
Exception Endianness. The value of this bit defines the value of the CPSR.E bit on entry to an
exception vector, including reset. This value also indicates the endianness of the translation table
data for translation table lookups:
0 Little endian.
B1 AArch32 system registers
B1.67 Hyp System Control Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English