ARM Cortex-A35

A.8 L2 error signals
The processor has signals for errors in the Level 2 cache.
Table A-10 L2 error signals
Signal Direction Description
nEXTERRIRQ Output
Error indicator for memory transactions with a write response error condition.
nINTERRIRQ Output
Error indicator for L2 RAM double-bit ECC error.
Related information
A7.5 Handling of external aborts on page A7-103
A Signal Descriptions
A.8 L2 error signals
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