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ARM Cortex-A35 User Manual

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C8.12 External Debug Peripheral Identification Register 3
The EDPIDR3 characteristics are:
Purpose
Provides information to identify an external debug component.
Usage constraints
This register is accessible as follows:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table C1-1 Conditions on external register access to debug registers on page C1-579 describes
the condition codes.
Configurations
The EDPIDR3 is in the Debug power domain.
Attributes
See C8.1 Memory-mapped debug register summary on page C8-644.
RES0
31 0
34
CMOD
78
REVAND
Figure C8-10 EDPIDR3 bit assignments
[31:8]
Reserved, RES0.
REVAND, [7:4]
0x0 Part minor revision.
CMOD, [3:0]
0x0 Customer modified.
The EDPIDR3 can be accessed through the external debug interface, offset 0xFEC.
C8 Memory-mapped debug registers
C8.12 External Debug Peripheral Identification Register 3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C8-661
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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