B1.78 Instruction Set Attribute Register 4
The ID_ISAR4 characteristics are:
Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR5. See:
• B1.74 Instruction Set Attribute Register 0 on page B1-269
• B1.75 Instruction Set Attribute Register 1 on page B1-271
• B1.76 Instruction Set Attribute Register 2 on page B1-273
• B1.77 Instruction Set Attribute Register 3 on page B1-275
• B1.79 Instruction Set Attribute Register 5 on page B1-279
Configurations
ID_ISAR4 is architecturally mapped to AArch64 register ID_ISAR4_EL1. See B2.61 AArch32
Instruction Set Attribute Register 4, EL1 on page B2-463.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_ISAR4 is a 32-bit register.
31
24 23 20 19 16 15 12 11 8 7 4 3 0
SynchPrim_frac
SWP_frac
28 27
PSR_M Barrier SMC Writeback WithShifts Unpriv
Figure B1-33 ID_ISAR4 bit assignments
SWP_frac, [31:28]
Indicates support for the memory system locking the bus for SWP or SWPB instructions:
0x0 SWP and SWPB instructions not implemented.
PSR_M, [27:24]
Indicates the implemented M profile instructions to modify the PSRs:
0x0 None implemented.
SynchPrim_frac, [23:20]
This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented
Synchronization Primitive instructions:
0x0 • The LDREX and STREX instructions.
• The CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.
• The LDREXD and STREXD instructions.
Barrier, [19:16]
B1 AArch32 system registers
B1.78 Instruction Set Attribute Register 4
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-277
Non-Confidential
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