Indicates the supported Barrier instructions in the A32 and T32 instruction sets:
0x1 The DMB, DSB, and ISB barrier instructions.
SMC, [15:12]
Indicates the implemented SMC instructions:
0x1 The SMC instruction.
Writeback, [11:8]
Indicates the support for writeback addressing modes:
0x1 Processor supports all of the writeback addressing modes defined in Armv8.
WithShifts, [7:4]
Indicates the support for instructions with shifts:
0x4 • Support for shifts of loads and stores over the range LSL 0-3.
• Support for other constant shift options, both on load/store and other instructions.
• Support for register-controlled shift options.
Unpriv, [3:0]
Indicates the implemented unprivileged instructions:
0x2 • The LDRBT, LDRT, STRBT, and STRT instructions.
• The LDRHT, LDRSBT, LDRSHT, and STRHT instructions.
To access the ID_ISAR4:
MRC p15, 0, <Rt>, c0, c2, 4 ; Read ID_ISAR4 into Rt
Register access is encoded as follows:
Table B1-61 ID_ISAR4 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 100
B1 AArch32 system registers
B1.78 Instruction Set Attribute Register 4
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-278
Non-Confidential
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