ARM Cortex-A35 User Manual

C8.18 External Debug Component Identification Register 2
The EDCIDR2 characteristics are:
Purpose
Provides information to identify an external debug component.
Usage constraints
This register is accessible as follows:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table C1-1 Conditions on external register access to debug registers on page C1-579 describes
the condition codes.
Configurations
The EDCIDR2 is in the Debug power domain.
Attributes
See C8.1 Memory-mapped debug register summary on page C8-644.
RES0
31 0
PRMBL_2
78
Figure C8-14 EDCIDR2 bit assignments
[31:8]
Reserved, RES0.
PRMBL_2, [7:0]
0x05 Preamble byte 2.
The EDCIDR2 can be accessed through the external debug interface, offset 0xFF8.
C8 Memory-mapped debug registers
C8.18 External Debug Component Identification Register 2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C8-667
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English